When a binary number is written to memory by a computer processor, the processor or external memory circuitry may append one or more additional bits for error checking, called parity bits. Typically, a single parity bit indicates whether the number of ones (or zeros) in a group of binary digits is odd or even. Likewise, when a group of binary digits is read from memory, the processor or external memory circuitry determines whether the number of ones (or zeros) in the data received is odd or even and compares the result to a received parity bit. If the received parity bit and the computed parity bit are different, an error must have occurred and other action is required.
A modern trend in processor design is to place more and more functionality onto a single integrated circuit. In particular, a processor integrated circuit may include internal cache memory to provide rapid access to the most recently used data. If cache memory is included on the processor chip, then parity encoding circuitry and parity decoding circuitry must also be on the chip. In addition, for optimal performance, it is desirable to be able to both read from a cache and write to a cache during a single clock cycle. Reading and writing during a single cycle typically requires parity encoding circuitry and parity decoding circuitry to be separate circuits. The requirement for separate circuits increases the amount of chip space consumed by parity encoding and decoding. There is a need for reducing the overall system circuitry by sharing parity circuitry for both encoding and decoding. There is a particular need for circuitry sharing when the parity circuitry is included within an integrated circuit processor and both memory reading and writing occur during a single clock cycle.